The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications. Pin Configurations. Microcontroller with 4 Kbytes Flash. Block Diagram.
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The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.
Pin Configurations. Microcontroller with 4 Kbytes Flash. Block Diagram. Description Continued. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.
Pin Description. Supply voltage. Port 0. As an output port each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-im- pedance inputs. In this mode P0 has internal pul- lups. Port 0 also receives the code bytes during Flash program- ming, and outputs the code bytes during program verifica- tion. External pullups are required during program verifica- tion. Port 1. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs.
As inputs, Port 1 pins that are externally being pulled low will source current I I L because of the internal pullups. Port 1 also receives the low-order address bytes during Flash programming and program verification. Port 2. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current I I L because of the internal pullups.
Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use bit addresses MOVX. In this application it uses strong internal pullups when emitting 1s.
Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Port 3. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current I I L because of the pullups. Port 3 also serves the functions of various special features of the AT89C51 as listed below:. Port Pin. Alternate Functions. INT0 extenal interrupt 0.
INT1 extenal interrupt 1 T0 timer 0 extenal input T1 timer 1 external input. WR extenal data memory write strobe. RD external data memory read strobe. Port 3 also receives some control signals for Flash pro- gramming and programming verification. Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.
Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no ef- fect if the microcrontroller is in external execution mode.
Program Store Enable is the read strobe to external pro- gram memory. When the AT89C51 is executing code from external pro- gram memory, PSEN is activated twice each machine cy- cle, except that two PSEN activations are skipped during each access to external data memory. External Access Enable. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.
EA should be strapped to V C C for internal program execu- tions. Input to the inverting oscillator amplifier and input to the internal clock operating circuit. Output from the inverting oscillator amplifier. Oscillator Characteristics. XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifi- cations must be observed.
Idle Mode. In idle mode, the CPU puts itself to sleep while all the on- chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the spe- cial functions registers remain unchanged during this. The idle mode can be terminated by any enabled interrupt or by a hardware reset.
It should be noted that when idle is terminated by a hard- ware reset, the device normally resumes program execu- tion, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hard-. Figure 1. Oscillator Connections. Program Memory.
Power Down. To eliminate the pos- sibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. Power Down Mode. In the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The only exit from power down is a hardware reset. The reset should not be activated before V C C.
Lock Bit Protection Modes. Program Memory Lock Bits. On the chip are three lock bits which can be left unpro- grammed U or can be programmed P to obtain the ad- ditional features listed in the table below:. When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a ran- dom value, and holds that value until reset is activated.
It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly. Program Lock Bits. Protection Type. No program lock features. MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, E A is sampled and latched on reset, and further programming of the Flash is disabled.
Same as mode 2, also verify is disabled. Same as mode 3, also external execution is disabled. Programming the Flash. The AT89C51 is normally shipped with the on-chip Flash. The programming interface accepts either a high-voltage volt or a low-voltage. V C C program enable signal. The low voltage program-. The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and device signature codes are listed in the following table.
Top-Side Mark. The AT89C51 code memory array is programmed byte- by-byte in either programming mode. To program any. Programming Algorithm: Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figures 3 and 4. To program the AT89C51, take the following steps.
Input the desired memory location on the address. Input the appropriate data byte on the data lines. Activate the correct combination of control signals. The byte-write cycle is self-timed and. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. During a write cycle, an at-.
8951 Microcontroller. Datasheet pdf. Equivalent
Note: The AT89C51 datasheet of the Microcontroller and more detailed Features can be found at the bottom of this page. The AT89C51 is an age old 8-bit microcontroller from the Atmel family. It works with the popular architecture and hence is used by most beginners till date. It is a 40 pin IC package with 4Kb flash memory. The AT89C51 is no longer in production and Atmel does not support new design. Instead the new AT89S51 is recommended for new applications.
atmel 8951 datasheet
8951 Datasheet PDF